Freescale Semiconductor /MKL27Z4 /I2S0 /MCR

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Interpret as MCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)MICS 0 (0)MOE 0 (0)DUF

DUF=0, MOE=0, MICS=00

Description

SAI MCLK Control Register

Fields

MICS

MCLK Input Clock Select

0 (00): MCLK divider input clock 0 selected.

1 (01): MCLK divider input clock 1 selected.

2 (10): MCLK divider input clock 2 selected.

3 (11): MCLK divider input clock 3 selected.

MOE

MCLK Output Enable

0 (0): MCLK signal pin is configured as an input that bypasses the MCLK divider.

1 (1): MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.

DUF

Divider Update Flag

0 (0): MCLK divider ratio is not being updated currently.

1 (1): MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

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